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PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
Rev. 01 -- 15 August 2005 Product data sheet
1. General description
The PCA9511A is a hot swappable I2C-bus and SMBus buffer that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card. When the connection is made, the PCA9511A provides bidirectional buffering, keeping the backplane and card capacitances isolated. The PCA9511A rise time accelerator circuitry allows the use of weaker DC pull-up currents while still meeting rise time requirements. The PCA9511A incorporates a digital ENABLE input pin, which enables the device when asserted HIGH and forces the device into a low current mode when asserted LOW, and an open-drain READY output pin, which indicates that the backplane and card sides are connected together (HIGH) or not (LOW). During insertion, the PCA9511A SDA and SCL lines are precharged to 1 V to minimize the current required to charge the parasitic capacitance of the chip.
2. Features
s Bidirectional buffer for SDA and SCL lines increases fan out and prevents SDA and SCL corruption during live board insertion and removal from multi-point backplane systems s Compatible with I2C-bus standard mode, I2C-bus fast mode, and SMBus standards s Built-in V/t rise time accelerators on all SDA and SCL lines (0.6 V threshold) s Active HIGH ENABLE input s Active HIGH READY open-drain output s High-impedance SDA and SCL pins for VCC = 0 V s 1 V precharge on all SDA and SCL lines s Supporting clock stretching and multiple master arbitration/synchronization s Operating power supply voltage range: 2.7 V to 5.5 V s 0 kHz to 400 kHz clock frequency s ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 s Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA s Packages offered: SO8, TSSOP8 (MSOP8)
3. Applications
s cPCI, VME, AdvancedTCA cards and other multi-point backplane cards that are required to be inserted or removed from an operating system
Philips Semiconductors
PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
4. Feature selection
Table 1: Feature idle detect high-impedance SDA, SCL pins for VCC = 0 V rise time accelerator circuitry on SDAn and SCLn lines rise time accelerator circuitry hardware disable pin for lightly loaded systems rise time accelerator threshold 0.8 V versus 0.6 V improves noise margin ready open-drain output Feature selection chart PCA9510A PCA9511A PCA9512A PCA9513A PCA9514A yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes -
two VCC pins to support 5 V to 3.3 V level translation with improved noise margins 1 V precharge on all SDA and SCL lines 92 A current source on SCLIN and SDAIN for PICMG applications in only -
5. Ordering information
Table 2: Ordering information Tamb = -40 C to +85 C Type number PCA9511AD PCA9511ADP
[1]
Topside mark PA9511A 9511A
Package Name SO8 TSSOP8 [1] Description plastic small outline package; 8 leads; body width 3.9 mm Version SOT96-1
plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1
Also known as `MSOP8'.
Standard packing quantities and other packaging data are available at www.standardics.philips.com/packaging/.
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Product data sheet
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PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
6. Block diagram
PCA9511A
2 mA 2 mA
SLEW RATE DETECTOR SDAIN CONNECT BACKPLANE-TO-CARD CONNECTION CONNECT ENABLE
SLEW RATE DETECTOR
VCC SDAOUT
CONNECT
100 k RCH1
100 k RCH3
1 VOLT PRECHARGE
100 k RCH2 2 mA 100 k RCH4 2 mA
SLEW RATE DETECTOR SCLIN CONNECT BACKPLANE-TO-CARD CONNECTION
SLEW RATE DETECTOR SCLOUT CONNECT 0.55VCC/ 0.45VCC STOP BIT AND BUS IDLE
0.5 A
0.55VCC/ 0.45VCC
20 pF
CONNECT 100 s DELAY UVLO READY RD S CONNECT
0.5 pF
UVLO ENABLE
QB
GND
002aab580
Fig 1. Block diagram of PCA9511A
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Product data sheet
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PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
7. Pinning information
7.1 Pinning
ENABLE SCLOUT SCLIN GND
1 2
8 7
VCC SDAOUT SDAIN READY
ENABLE SCLOUT SCLIN GND
1 2 3 4
002aab578
8 7
VCC SDAOUT SDAIN READY
PCA9511AD
3 4
002aab577
6 5
PCA9511ADP
6 5
Fig 2. Pin configuration for SO8
Fig 3. Pin configuration for TSSOP8
7.2 Pin description
Table 3: Symbol ENABLE Pin description Pin 1 Description Chip enable. Grounding this input puts the part in a low current (< 1 A) mode. It also disables the rise time accelerators, isolates SDAIN from SDAOUT and isolates SCLIN from SCLOUT. serial clock output to and from the SCL bus on the card serial clock input to and from the SCL bus on the backplane Ground. Connect this pin to a ground plane for best results. open-drain output which pulls LOW when SDAIN and SCLIN are disconnected from SDAOUT and SCLOUT, and goes HIGH when the two sides are connected serial data input to and from the SDA bus on the backplane serial data output to and from the SDA bus on the card power supply
SCLOUT SCLIN GND READY
2 3 4 5
SDAIN SDAOUT VCC
6 7 8
8. Functional description
Refer to Figure 1 "Block diagram of PCA9511A".
8.1 Start-up
An undervoltage/initialization circuit holds the parts in a disconnected state which presents high-impedance to all SDA and SCL pins during power-up. A LOW on the ENABLE pin also forces the parts into the low current disconnected state when the ICC is essentially zero. As the power supply is brought up and the ENABLE is HIGH or the part is powered and the ENABLE is taken from LOW to HIGH it enters an initialization state where the internal references are stabilized and the precharge circuit is enabled. At the end of the initialization state the `Stop Bit And Bus Idle' detect circuit is enabled. With the ENABLE pin HIGH long enough to complete the initialization state (ten) and remaining HIGH when all the SDA and SCL pins have been HIGH for the bus idle time or when all pins are HIGH and a STOP condition is seen on the SDAIN and SCLIN pins, SDAIN is connected to SDAOUT and SCLIN is connected to SCLOUT. The 1 V precharge circuitry
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PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
is activated during the initialization and is deactivated when the connection is made. The precharge circuitry pulls up the SDA and SCL pins to 1 V through individual 100 k nominal resistors. This precharges the pins to 1 V to minimize the worst case disturbances that result from inserting a card into the backplane where the backplane and the card are at opposite logic levels.
8.2 Connect circuitry
Once the connection circuitry is activated, the behavior of SDAIN and SDAOUT as well as SCLIN and SCLOUT become identical with each acting as a bidirectional buffer that isolates the input capacitance from the output bus capacitance while communicating the logic levels. A LOW forced on either SDAIN or SDAOUT will cause the other pin to be driven to a LOW by the part. The same is also true for the SCL pins. Noise between 0.7VCC and VCC is generally ignored because a falling edge is only recognized when it falls below 0.7VCC with a slew rate of at least 1.25 V/s. When a falling edge is seen on one pin, the other pin in the pair turns on a pull-down driver that is referenced to a small voltage above the falling pin. The driver will pull the pin down at a slew rate determined by the driver and the load initially, because it does not start until the first falling pin is below 0.7VCC. The first falling pin may have a fast or slow slew rate, if it is faster than the pull down slew rate then the initial pull-down rate will continue. If the first falling pin has a slow slew rate then the second pin will be pulled down at its initial slew rate only until it is just above the first pin voltage then they will both continue down at the slew rate of the first. Once both sides are LOW they will remain LOW until all the external drivers have stopped driving LOWs. If both sides are being driven LOW to the same value for instance, 10 mV by external drivers, which is the case for clock stretching and is typically the case for acknowledge, and one side external driver stops driving that pin will rise until the internal driver pulls it down to the offset voltage. When the last external driver stops driving a LOW, that pin will rise up and settle out just above the other pin as both rise together with a slew rate determined by the internal slew rate control and the RC time constant. As long as the slew rate is at least 1.25 V/s, when the pin voltage exceeds 0.6 V for the PCA9511A, the rise time accelerator's circuits are turned on and the pull-down driver is turned off.
8.3 Maximum number of devices in series
Each buffer adds about 0.1 V dynamic level offset at 25 C with the offset larger at higher temperatures. Maximum offset (Voffset) is 0.150 V with a 10 k pull-up resistor. The LOW level at the signal origination end (master) is dependent upon the load and the only specification point is the I2C-bus specification of 3 mA will produce VOL < 0.4 V, although if lightly loaded the VOL may be 0.1 V. Assuming VOL = 0.1 V and Voffset = 0.1 V, the level after four buffers would be 0.5 V, which is only about 0.1 V below the threshold of the rising edge accelerator (about 0.6 V). With great care a system with four buffers may work, but as the VOL moves up from 0.1 V, noise or bounces on the line will result in firing the rising edge accelerator thus introducing false clock edges. Generally it is recommended to limit the number of buffers in series to two, and to keep the load light to minimize the offset. The PCA9510A (rise time accelerator is permanently disabled) and the PCA9512A (rise time accelerator can be turned off) are a little different with the rise time accelerator turned off because the rise time accelerator will not pull the node up, but the same logic that turns
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PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
on the accelerator turns the pull-down off. If the VIL is above 0.6 V and a rising edge is detected, the pull-down will turn off and will not turn back on until a falling edge is detected.
buffer A MASTER common node
buffer B SLAVE B
buffer C SLAVE C
002aab581
Fig 4. System with 3 buffers connected to common node
Consider a system with three buffers connected to a common node and communication between the Master and Slave B that are connected at either end of buffer A and buffer B in series as shown in Figure 4. Consider if the VOL at the input of buffer A is 0.3 V and the VOL of Slave B (when acknowledging) is 0.4 V with the direction changing from Master to Slave B and then from Slave B to Master. Before the direction change you would observe VIL at the input of buffer A of 0.3 V and its output, the common node, is 0.4 V. The output of buffer B and buffer C would be 0.5 V, but Slave B is driving 0.4 V, so the voltage at Slave B is 0.4 V. The output of buffer C is 0.5 V. When the Master pull-down turns off, the input of buffer A rises and so does its output, the common node, because it is the only part driving the node. The common node will rise to 0.5 V before buffer B's output turns on, if the pull-up is strong the node may bounce. If the bounce goes above the threshold for the rising edge accelerator 0.6 V the accelerators on both buffer A and buffer C will fire contending with the output of buffer B. The node on the input of buffer A will go HIGH as will the input node of buffer C. After the common node voltage is stable for a while the rising edge accelerators will turn off and the common node will return to 0.5 V because the buffer B is still on. The voltage at both the Master and Slave C nodes would then fall to 0.6 V until Slave B turned off. This would not cause a failure on the data line as long as the return to 0.5 V on the common node (0.6 V at the Master and Slave C) occurred before the data setup time. If this were the SCL line, the parts on buffer A and buffer C would see a false clock rather than a stretched clock, which would cause a system error.
8.4 Propagation delays
The delay for a rising edge is determined by the combined pull-up current from the bus resistors and the rise time accelerator current source and the effective capacitance on the lines. If the pull-up currents are the same, any difference in rise time is directly proportional to the difference in capacitance between the two sides. The tPLH may be negative if the output capacitance is less than the input capacitance and would be positive if the output capacitance is larger than the input capacitance, when the currents are the same. The tPHL can never be negative because the output does not start to fall until the input is below 0.7VCC, and the output turn on has a non-zero delay, and the output has a limited maximum slew rate, and even if the input slew rate is slow enough that the output catches up it will still lag the falling voltage of the input by the offset voltage. The maximum tPHL occurs when the input is driven LOW with zero delay and the output is still limited by its
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PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
turn-on delay and the falling edge slew rate. The output falling edge slew rate is a function of the internal maximum slew rate which is a function of temperature, VCC and process, as well as the load current and the load capacitance.
8.5 Rise time accelerators
During positive bus transitions a 2 mA current source is switched on to quickly slew the SDA and SCL lines HIGH once the input level of 0.6 V for the PCA9511A is exceeded. The rising edge rate should be at least 1.25 V/s to guarantee turn on of the accelerators.
8.6 READY digital output
This pin provides a digital flag which is LOW when either ENABLE is LOW or the start-up sequence described earlier in this section has not been completed. READY goes HIGH when ENABLE is HIGH and start-up is complete. The pin is driven by an open-drain pull-down capable of sinking 3 mA while holding 0.4 V on the pin. Connect a resistor of 10 k to VCC to provide the pull-up.
8.7 ENABLE low current disable
Grounding the ENABLE pin disconnects the backplane side from the card side, disables the rise-time accelerators, drives READY LOW, disables the bus precharge circuitry, and puts the part in a low current state. When the pin voltage is driven all the way to VCC, the part waits for data transactions on both the backplane and card sides to be complete before reconnecting the two sides.
8.8 Resistor pull-up value selection
The system pull-up resistors must be strong enough to provide a positive slew rate of 1.25 V/s on the SDA and SCL pins, in order to activate the boost pull-up currents during rising edges. Choose maximum resistor value using the formula:
3 V CC ( min ) - 0.6 R 800 x 10 ---------------------------------- - C
where R is the pull-up resistor value in , VCC(min) is the minimum VCC voltage in volts, and C is the equivalent bus capacitance in picofarads (pF). In addition, regardless of the bus capacitance, always choose R 16 k for VCC = 5.5 V maximum, R 24 k for VCC = 3.6 V maximum. The start-up circuitry requires logic HIGH voltages on SDAOUT and SCLOUT to connect the backplane to the card, and these pull-up values are needed to overcome the precharge voltage. See the curves in Figure 5 and Figure 6 for guidance in resistor pull-up selection.
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PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
30 RPU (k) Rmax = 24 k 20
002aab582
20 RPU (k) 15
002aab583
Rmax = 16 k rise time > 300 ns
10 rise time > 300 ns 10 recommended pull-up 5 recommended pull-up
0 0 100 200 300 Cb (pF) 400
0 0 100 200 300 Cb (pF) 400
Fig 5. Bus requirements for 3.3 V systems
Fig 6. Bus requirements for 5 V systems
8.9 Hot swapping and capacitance buffering application
Figure 7 through Figure 10 illustrate the usage of the PCA9511A in applications that take advantage of both its hot swapping and capacitance buffering features. In all of these applications, note that if the I/O cards were plugged directly into the backplane, all of the backplane and card capacitances would add directly together, making rise time and fall time requirements difficult to meet. Placing a bus buffer on the edge of each card, however, isolates the card capacitance from the backplane. For a given I/O card, the PCA9511A drives the capacitance of everything on the card and the backplane must drive only the capacitance of the bus buffer, which is less than 10 pF, the connector, trace, and all additional cards on the backplane. See Application Note AN10160, `Hot Swap Bus Buffer' for more information on applications and technical assistance.
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Product data sheet
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PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
BACKPLANE CONNECTOR
BACKPLANE STAGGERED CONNECTOR VCC
R1 10 k R2 10 k
I/O PERIPHERAL CARD 1 POWER SUPPLY HOT SWAP
R3 10 k C1 0.01 F
R4 10 k
R5 10 k
R6 10 k
BD_SEL SDA SCL
ENABLE SDAIN SCLIN
VCC
GND
SDAOUT SCLOUT READY
CARD1_SDA CARD1_SCL
I/O PERIPHERAL CARD 2 STAGGERED CONNECTOR POWER SUPPLY HOT SWAP
R7 10 k C3 0.01 F
R8 10 k
R9 10 k
R10 10 k
ENABLE SDAIN SCLIN
VCC
GND
SDAOUT SCLOUT READY
CARD2_SDA CARD2_SCL
I/O PERIPHERAL CARD N STAGGERED CONNECTOR POWER SUPPLY HOT SWAP
R11 10 k C5 0.01 F
R12 10 k
R13 10 k
R14 10 k
ENABLE SDAIN SCLIN
VCC
GND
SDAOUT SCLOUT READY
CARDN_SDA CARDN_SCL
002aab584
Remark: The PCA9511A can be used in any combination depending on the number of rise time accelerators that are needed by the system. Normally only one PCA9511A would be required per bus.
Fig 7. Hot swapping multiple I/O cards into a backplane using the PCA9511A in a cPCI, VME, and AdvancedTCA system
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PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
BACKPLANE CONNECTOR
BACKPLANE VCC
R1 10 k R2 10 k
I/O PERIPHERAL CARD 1 STAGGERED CONNECTOR
C1 0.01 F
R4 10 k
R5 10 k
R6 10 k
SDA SCL
C2 0.01 F
ENABLE SDAIN SCLIN
VCC
GND
SDAOUT SCLOUT READY
CARD1_SDA CARD1_SCL
I/O PERIPHERAL CARD 2 STAGGERED CONNECTOR
C3 0.01 F
R8 10 k
R9 10 k
R10 10 k
C4 0.01 F
ENABLE SDAIN SCLIN
VCC
GND
SDAOUT SCLOUT READY
CARD2_SDA CARD2_SCL
002aab585
Fig 8. Hot swapping multiple I/O cards into a backplane using the PCA9511A in a PCI system
I2C-bus System 1 VCC = 5 V
R1 10 k R4 10 k C1 0.01 F R5 10 k R2 1 k R3 1 k R6 10 k
I2C-bus System 2 VCC
C2 0.01 F R7 10 k R8 10 k
to other System 1 devices
SDA1 SCL1
VCC ENABLE SDAOUT SDAIN SCLOUT SCLIN READY GND
VCC SDAOUT ENABLE SCLOUT SDAIN READY SCLIN GND
SDA1 SCL1
long distance bus
to other System 2 devices
002aab586
Remark: See Application Note AN255, `I2C repeaters, hubs, and expanders' for more information on other devices better optimized for long distance transmission of the I2C-bus or SMBus.
Fig 9. Repeater/bus extender application using the PCA9511A
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PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
Rdrop
VCC
R1 10 k R4 10 k
VCC_LOW
C2 0.01 F R2 1 k R3 1 k R5 10 k
SDA SCL
VCC ENABLE SDAOUT SDAIN SCLOUT SCLIN READY GND
SDA2 SCL2
002aab587
VCC > VCC_LOW Rdrop is the line loss of VCC in the backplane.
Fig 10. System with disparate VCC voltages
9. Application design-in information
VCC (2.7 V to 5.5 V)
R1 10 k
R2 10 k
C1 0.01 F
8
R5 10 k
R3 10 k
R4 10 k
SCLIN
3
2
SCLOUT
SDAIN
6
7
SDAOUT
ENABLE
1
ENABLE GND 4
READY
5
002aab579
Fig 11. Typical application
10. Limiting values
Table 4: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC Vn Toper Tstg Tsp Tj(max)
[1]
9397 750 13269
Parameter supply voltage voltage on SDAIN, SCLIN, SDAOUT, SCLOUT, READY, ENABLE operating temperature storage temperature solder point temperature maximum junction temperature
Conditions
[1] [1]
Min -0.5 -0.5 -40 -65
Max +7 +7 +85 +150 +300 +125
Unit V V C C C C
10 s max.
-
Voltages with respect to pin GND.
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PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
11. Characteristics
Table 5: Characteristics VCC = 2.7 V to 5.5 V; Tamb = -40 C to +85 V; unless otherwise specified. Symbol VCC ICC ICC(sd) Parameter supply voltage supply current VCC = 5.5 V; VSDAIN = VSCLIN = 0 V Conditions
[1] [1]
Min 2.7 -
Typ 3.5 0.1
Max 5.5 6 -
Unit V mA A
Power supply
Shut-down mode supply VENABLE = 0 V; all other pins at current VCC or GND precharge voltage SDA, SCL floating
[1]
Start-up circuitry Vpch 0.8 0.3 x VCC VENABLE = 0 V to VCC
[2] [1]
1.1
1.2
V
VIH(ENABLE) HIGH-state input voltage on pin ENABLE VIL(ENABLE) LOW-state input voltage on pin ENABLE II(ENABLE) ten tidle(READY) tdis(EN-RDY) tstp(READY) tREADY ILZ(READY) Ci(ENABLE) Co(READY) input current on pin ENABLE enable time bus idle time to READY active disable time (ENABLE to READY) SDAIN to READY delay after STOP SCLOUT/SDAOUT to READY off-state leakage current VENABLE = VCC on pin READY input capacitance on pin VI = VCC or GND ENABLE output capacitance on pin READY VI = VCC or GND Ipu = 3 mA; VENABLE = VCC
[4] [3]
0.5 x VCC 0.7 x VCC V 0.5 x VCC 0.1 110 105 30 1.2 0.8 0.3 1.9 2.5 1 200 4.0 4.0 0.4 V A s s ns s s A pF pF V
50 -
[3]
[4]
VOL(READY) LOW-state output voltage on pin READY Rise time accelerators Itrt(pu)
[1]
transient boosted pull-up positive transition on SDA, SCL; current VCC = 2.7 V; slew rate = 1.25 V/s
[5]
1
2
-
mA
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PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
Table 5: Characteristics ...continued VCC = 2.7 V to 5.5 V; Tamb = -40 C to +85 V; unless otherwise specified. Symbol Voffset tPLH Parameter offset voltage Conditions 10 k to VCC on SDA, SCL; VCC = 3.3 V
[1] [6] [8]
Min 0 -
Typ 110 0
Max 175 -
Unit mV ns
Input-output connection
LOW-to-HIGH 10 k to VCC; propagation delay (SCL CL = 100 pF each side to SCL and SDA to SDA) HIGH-to-LOW 10 k to VCC; propagation delay (SCL CL = 100 pF each side to SCL and SDA to SDA)
[4]
tPHL
-
70
-
ns
Ci(SCL/SDA) SCL and SDA input capacitance VOL ILI fSCL tBUF LOW-state output voltage input leakage current SCL clock frequency bus free time between STOP and START condition START condition hold time START condition set-up time STOP condition set-up time data hold time data setup time SCL LOW time SCL HIGH time fall time SDA and SCL rise time SDA and SCL
This specification applies over the full operating temperature range.
0 -1
5 -
7 0.4 +1 400 -
pF V A kHz s
VI = 0 V; SDAn, SCLn pins; Isink = 3 mA; VCC = 2.7 V SDAn, SCLn pins; VCC = 5.5 V
[1]
System characteristics
[4] [4]
0 1.3
tHD;STA tSU;STA tSU;STO tHD;DAT tSU;DAT tLOW tHIGH tf tr
[1] [2] [3] [4] [5] [6] [7] [8]
[4]
0.6 0.6 0.6 300 100 1.3 0.6 20 + 0.1 x Cb 20 + 0.1 x Cb
-
300 300
s s s ns ns s s ns ns
[4]
[4]
[4] [4] [4] [4] [4] [7] [4] [7]
The enable time can slow considerably for some parts when temperature is < -20 C. Delays that can occur after ENABLE and/or idle times have passed. Guaranteed by design, not production tested. Itrt(pu) varies with temperature and VCC voltage, as shown in Section 11.1 "Typical performance characteristics". The connection circuitry always regulates its output to a higher voltage than its input. The magnitude of this offset voltage as a function of the pull-up resistor and VCC voltage is shown in Section 11.1 "Typical performance characteristics". Cb = total capacitance of one bus line in pF. Force VSDAIN = VSCLIN = 0.1 V, tie SDAOUT and SCLOUT through 10 k resistor to VCC and measure the SDAOUT and SCLOUT output.
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PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
11.1 Typical performance characteristics
3.7 ICC (mA) 3.3
002aab588
12 Itrt(pu) (mA) 8
002aab590
VCC = 5.5 V
3.3 V 2.7 V
VCC = 5 V
2.9
4 3.0 V 2.7 V
2.5 -40
+25 Tamb (C)
+90
0 -40
+25 Tamb (C)
+90
Fig 12. ICC versus temperature
90 VCC = 5.5 V tPHL (ns) 80
002aab589
Fig 13. Itrt(pu) versus temperature
300 V O - VI (mV) 200 VCC = 5 V
002aab591
2.7 V 3.3 V
70
100 3.3 V
60 -40
0 +25 Tamb (C) +90 0 10000 20000 30000 40000 RPU ()
Ci = Co > 100 pF; RPU(in) = RPU(out) = 10 k
Fig 14. Input/output tPHL versus temperature
Fig 15. Connection circuitry VO - VI
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Philips Semiconductors
PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
11.2 Timing diagrams
SDAn/SCLn
ten ENABLE tidle(READY) READY
002aab592
tdis
Fig 16. Timing for ten, tidle(READY), and tdis
SDAIN
SCLIN SCLOUT SDAOUT ten ENABLE tstp(READY) READY
002aab593
tstp(READY) is only applicable after the ten delay.
Fig 17. tstp(READY) that can occur after ten
SCLIN, SDAIN
SCLOUT, SDAOUT ten tidle(READY) ENABLE tstp(READY) READY
002aab594
tstp(READY) is only applicable after the ten delay.
Fig 18. tstp(READY) delay that can occur after ten and tidle(READY)
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Product data sheet
Rev. 01 -- 15 August 2005
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Philips Semiconductors
PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
12. Test information
VCC VCC PULSE GENERATOR VI D.U.T.
RT CL 100 pF RL 10 k
VO
002aab595
RL = load resistor CL = load capacitance includes jig and probe capacitance RT = termination resistance should be equal to the output impedance Z0 of the pulse generators.
Fig 19. Test circuitry for switching times
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(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 15 August 2005
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Philips Semiconductors
PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
13. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
D
E
A X
c y HE vMA
Z 8 5
Q A2 A1 pin 1 index Lp 1 e bp 4 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.010 0.057 0.004 0.049
0.019 0.0100 0.014 0.0075
0.244 0.039 0.028 0.041 0.228 0.016 0.024
8o o 0
ISSUE DATE 99-12-27 03-02-18
Fig 20. Package outline SOT96-1 (SO8)
9397 750 13269 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 15 August 2005
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Philips Semiconductors
PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
D
E
A
X
c y HE vMA
Z
8
5
A2 pin 1 index
A1
(A3)
A
Lp L
1
e bp
4
detail X wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.45 0.25 c 0.28 0.15 D(1) 3.1 2.9 E(2) 3.1 2.9 e 0.65 HE 5.1 4.7 L 0.94 Lp 0.7 0.4 v 0.1 w 0.1 y 0.1 Z(1) 0.70 0.35 6 0
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT505-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18
Fig 21. Package outline SOT505-1 (TSSOP8)
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Product data sheet
Rev. 01 -- 15 August 2005
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Philips Semiconductors
PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
14. Soldering
14.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
14.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
14.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
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Product data sheet
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Philips Semiconductors
PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
- smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
14.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
14.5 Package related soldering information
Table 6: Package [1] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8], PMFP [9], WQCCN..L [8]
[1] [2]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable [4] Reflow [2] suitable suitable
suitable not not recommended [5] [6] recommended [7]
suitable suitable suitable not suitable
not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.
[3]
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Product data sheet
Rev. 01 -- 15 August 2005
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Philips Semiconductors
PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
[4]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages.
[5] [6] [7] [8]
[9]
15. Abbreviations
Table 7: Acronym AdvancedTCA CDM cPCI ESD HBM I2C-bus MM PCI PICMG SMBus VME Abbreviations Description Advanced Telecommunications Computing Architecture Charged Device Model compact Peripheral Component Interface Electrostatic Discharge Human Body Model Inter IC bus Machine Model Peripheral Component Interface PCI Industrial Computer Manufacturers Group System Management Bus VERSAModule Eurocard
16. Revision history
Table 8: Revision history Release date 20050815 Data sheet status Product data sheet Change notice Doc. number 9397 750 13269 Supersedes Document ID PCA9511A_1
9397 750 13269
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 15 August 2005
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Philips Semiconductors
PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
17. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
18. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
20. Trademarks
Notice -- All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- wordmark and logo are trademarks of Koninklijke Philips Electronics N.V.
19. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
21. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
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(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 15 August 2005
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Philips Semiconductors
PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
22. Contents
1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9 10 11 11.1 11.2 12 13 14 14.1 14.2 14.3 14.4 14.5 15 16 17 18 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Feature selection . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Start-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connect circuitry. . . . . . . . . . . . . . . . . . . . . . . . 5 Maximum number of devices in series . . . . . . . 5 Propagation delays . . . . . . . . . . . . . . . . . . . . . . 6 Rise time accelerators . . . . . . . . . . . . . . . . . . . 7 READY digital output . . . . . . . . . . . . . . . . . . . . 7 ENABLE low current disable. . . . . . . . . . . . . . . 7 Resistor pull-up value selection . . . . . . . . . . . . 7 Hot swapping and capacitance buffering application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Application design-in information . . . . . . . . . 11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12 Typical performance characteristics . . . . . . . . 14 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 15 Test information . . . . . . . . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 19 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 19 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 20 Package related soldering information . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 22 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Contact information . . . . . . . . . . . . . . . . . . . . 22
(c) Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 15 August 2005 Document number: 9397 750 13269
Published in The Netherlands

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